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ds07-12505-3e fujitsu semiconductor data sheet 8-bit proprietary microcontroller cmos f 2 mc-8l mb89640 series mb89643/645/646/647/p647/pv640 n description the mb89640 series has been developed as a general-purpose version of the f 2 mc*-8l family consisting of proprietary 8-bit, single-chip microcontrollers. in addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions such as dual-clock control system, five operating speed control stages, timers, a pwm timer, serial interface, an a/d converter, a d/a converter, an external interrupt, and a watch prescaler. *: f 2 mc stands for fujitsu flexible microcontroller. n features ?f 2 mc-8l family cpu core instruction set optimized for controllers (continued) n pac k ag e multiplication and division instructions 16-bit arithmetic operations test and branch instructions bit manipulation instructions, etc. (fpt-80p-m11) (fpt-80p-m06) (mqp-80c-p01) 80-pin plastic qfp 80-pin plastic qfp 80-pin ceramic mqfp
2 mb89640 series (continued) ? six types of timers 8-bit pwm timer: 2 channels (also usable reload timer) 8-bit pulse width counter (continuous measurement capable and applicable to remote control) 16-bit timer/counter 21-bit time-base counter 15-bit watch prescaler ? two 8-bit serial i/o swichable transfer direction allows communication with various equipment. ? 8-bit a/d converter: 8 channels sense mode function enabling comparison at 12 instructions activation by external input capable ? external interrupt 1, external interrupt 2: 9 channels ? 8-bit d/a converter: 2 channels 8-bit r-2r type ? low-power consumption modes (stop mode, sleep mode, watch mode, subclock mode) ? bus interface functions including hold and ready functions
3 mb89640 series n product lineup (continued) mb89643 mb89645 mb89646 mb89647 MB89P647 mb89pv640 classification mass production products (mask rom products) one-time prom product piggyback/ evaluation product for evaluation and development rom size 8 k 8 bits (internal mask rom) 16 k 8 bits (internal mask rom) 24 k 8 bits (internal mask rom) 32 k 8 bits (internal mask rom) 32 k 8 bits (internal prom, programming with general-purpose programmer) 32 k 8 bits (external rom) ram size 256 8 bits 512 8 bits 768 8 bits 1 k 8 bits cpu functions number of instructions: 136 instruction bit length: 8 bits instruction length: 1 to 3 bytes data bit length: 1, 8, 16 bits minimum execution time: 0.4 m s/10 mhz to 6.4 m s/10 mhz, or 61.0 m s/32.768 khz interrupt processing time: 3.6 m s/10 mhz to 57.6 m s/10 mhz, or 562.5 m s/32.768 khz ports input ports (cmos): 9 (all also serve as a external interrupt.) output ports (cmos): 8 (all also serve as a bus control.) i/o ports (cmos): 24 (8 ports also serve as peripherals, 16 ports also serve as a bus control.) i/o ports (n-ch open-drain): 8 (all also serve as peripherals.) output ports (n-ch open-drain): 16 (8 ports also serve as peripherals.) total: 65 clock timer 21 bits 1 (in main clock mode), 15 bits 1 (at 32.768 khz) 8-bit pwm timer 8-bit reload timer operation 2 channels 7/8-bit resolution pwm operation 2 channels 8-bit ppg operation 1 channel 8-bit pulse width counter 8-bit timer operation (overflow output capable) 8-bit reload timer operation (toggled output capable) 8-bit pulse width measurement operation (continuous measurement capable, measurement of h width/l width/from - to /from to - capable) 16-bit timer/ counter 16-bit timer operation 16-bit event counter operation 8-bit serial i/o 8 bits 2 channels lsb first/msb first selectability one clock selectable from four transfer clocks (one external shift clock, three internal shift clocks: 0.8 m s, 3.2 m s, 12.8 m s) 8-bit a/d converter 8-bit resolution 8 channels a/d conversion mode (conversion time: 44 instructions) sense mode (conversion time: 12 instructions) continuous activation by an external activation or an internal timer capable reference voltage input part number parameter
4 mb89640 series (continued) *1: varies with conditions such as the operating frequency. (see section n electrical characteristics.) n package and corresponding products : available : not available note: for more information about each package, see section n external dimensions. mb89643 mb89645 mb89646 mb89647 MB89P647 mb89pv640 8-bit d/a converter 8-bit resolution 2 channels, r-2r type external interrupt 1, external interrupt 2 9 channels standby modes watch mode, subclock mode, sleep mode, and stop mode process cmos operating voltage* 1 2.2 v to 6.0 v 2.7 v to 6.0 v eprom for use ? mbm27c256a -20tv package mb89643 mb89645 mb89646 mb89647 MB89P647 mb89pv640 fpt-80p-m11 fpt-80p-m06 mqp-80c-p01 part number parameter
5 mb89640 series n differences among products 1. memory size before evaluating using the piggyback product, verify its differences from the product that will actually be used. take particular care on the following points: ? on the mb89643 register banks 16 to 32 cannot be used. ? on the MB89P647, the program area starts from address 8007 h but on the mb89pv640 and mb89647 starts from 8000 h . (on the MB89P647, addresses 8000 h to 8006 h comprise the option setting area, option settings can be read by reading these addresses. on the mb89pv640 and mb89647, addresses 8000 h to 8006 h could also be used as a program rom. however, do not use these addresses in order to maintain compatibility of the MB89P647.) ? the stack area, etc., is set at the upper limit of the ram. ? the external areas are used. 2. current consumption ? in the case of the mb89pv640, add the current consumed by the eprom which is connected to the top socket. ? when operated at low speed, the product with an otprom (one-time prom) or an eprom will consume more current than the product with a mask rom. ? however, the current consumption in sleep/stop modes is the same. (for more information, see sections n electrical characteristics and n example characteristics.) 3. mask options functions that can be selected as options and how to designate these options vary by the product. before using options check section n mask options. take particular care on the following points: ? a pull-up resistor cannot be set for p40 to p47 and p50 to p57 on the MB89P647. ? for all products, p60 to p67 are available for no pull-up resistor when an a/d converter is used. ? for all products, p50 to p57 are available for no pull-up resistor when a d/a converter is used. ? options are fixed on the mb89pv640.
6 mb89640 series n pin assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 p71/li1 p70/li0 p83/int3 p82/int2 p81/int1 p80/int0 x0a x1a mod0 mod1 x0 x1 v ss rst p27/ale p26/rd p25/wr p24/clk p23/rdy p22/hrq 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p54/bz p55/sck2 p56/so2 p57/si2 v ss p40 p41 v cc p42 p43 p44 p45 p46 p47 p30/adst p31/sck1 p32/so1 p33/si1 p34/ec p35/pwc 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 p72/li2 p73/li3 p74/li4 p60/an0 p61/an1 p62/an2 p63/an3 p64/an4 p65/an5 p66/an6 p67/an7 av ss avrl avrh av cc davc p50/da1 p51/da2 p52/pwm p53/pto2 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p21/hak p20/bufc p17/a15 p16/a14 p15/a13 p14/a12 p13/a11 p12/a10 p11/a09 p10/a08 p07/ad7 p06/ad6 p05/ad5 p04/ad4 p03/ad3 p02/ad2 p01/ad1 p00/ad0 p37/pto1 p36/wto (fpt-80p-m11) (top view)
7 mb89640 series ? pin assignment on package top (mb89pv640 only) n.c.: internally connected. do not use. pin no. pin name pin no. pin name pin no. pin name pin no. pin name 81 n.c. 89 a2 97 n.c. 105 oe 82 v pp 90 a1 98 o4 106 n.c. 83a1291a099o5107a11 84 a7 92 n.c. 100 o6 108 a9 85 a6 93 o1 101 o7 109 a8 86 a5 94 o2 102 o8 110 a13 87 a4 95 o3 103 ce 111 a14 88 a3 96 v ss 104 a10 112 v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 p73/li3 p72/li2 p71/li1 p70/li0 p83/int3 p82/int2 p81/int1 p80/int0 x0a x1a mod0 mod1 x0 x1 v ss rst p27/ale p26/rd p25/wr p24/clk p23/rdy p22/hrq p21/hak p20/bufc 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p52/pwm p53/pto2 p54/bz p55/sck2 p56/so2 p57/si2 v ss p40 p41 v cc p42 p43 p44 p45 p46 p47 p30/adst p31/sck1 p32/so1 p33/si1 p34/ec p35/pwc p36/wto p37/pto1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 p74/li4 p60/an0 p61/an1 p62/an2 p63/an3 p64/an4 p65/an5 p66/an6 p67/an7 av ss avrl avrh av cc davc p50/da1 p51/da2 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p17/a15 p16/a14 p15/a13 p14/a12 p13/a11 p12/a10 p11/a09 p10/a08 p07/ad7 p06/ad6 p05/ad5 p04/ad4 p03/ad3 p02/ad2 p01/ad1 p00/ad0 101 102 103 104 105 106 107 108 109 93 92 91 90 89 88 87 86 85 100 99 98 97 96 95 94 110 111 112 81 82 83 84 (top view) (fpt-80p-m06) (mqp-80c-p01) each pin inside the dashed line is for the mb89pv640 only.
8 mb89640 series n pin description (continued) *1: fpt-80p-m11 *2: fpt-80p-m06 *3: mqp-80c-p01 pin no. pin name circuit type function qfp *1 qfp *2 mqfp *3 11 13 x0 a main clock crystal oscillator pins (max. 10 mhz) 12 14 x1 9 11 mod0 c operating mode selection pins connect directly to v cc or v ss . 10 12 mod1 14 16 rst d reset i/o pin this pin is an n-ch open-drain output type with pull-up resistor, and a hysteresis input type. l is output from this pin by an internal reset source. the internal circuit is initialized by the input of l. 38 to 31 40 to 33 p00/ad0 to p07/ad7 e general-purpose i/o ports also serve as multiplex pins of lower address output and data i/o. 30 to 23 32 to 25 p10/a08 to p17/a15 e general-purpose i/o ports also serve as an upper address output. 22, 21, 18, 15 24, 23, 20, 17 p20/bufc, p21/hak , p24/clk, p27/ale g general-purpose output-only ports also serve as a bus control signal output. 20, 19 22, 21 p22/hrq, p23/rdy e general-purpose output-only ports also serve as a bus control signal input. 17, 16 19, 18 p25/wr , p26/rd e general-purpose output-only ports also serve as a bus control signal output. 46 48 p30/adst f general-purpose i/o port also serves as an a/d converter external activation. this port is a hysteresis input type. 45 47 p31/sck1 f general-purpose i/o port also serves as the clock i/o for the serial i/o 1. this port is a hysteresis input type. 44, 43 46, 45 p32/so1, p33/si1 f general-purpose i/o ports also serve as the data output for the serial i/o 1. these ports are a hysteresis input type. 42 44 p34/ec f general-purpose i/o port also serves as the external clock input for the 16-bit timer/ counter. this port is a hysteresis input type.
9 mb89640 series (continued) *1: fpt-80p-m11 *2: fpt-80p-m06 *3: mqp-80c-p01 pin no. pin name circuit type function qfp *1 qfp *2 mqfp *3 41 43 p35/pwc f general-purpose i/o port also serves as the measured pulse input for the 8-bit pulse width counter. this port is a hysteresis input type. 40 42 p36/wto f general-purpose i/o port also serves as the toggle output for the 8-bit pulse width counter. this port is a hysteresis input type. 39 41 p37/pto1 f general-purpose i/o port also serves as the toggle output for the 1-channel pwm timer. 55, 54, 52 to 47 57, 56, 54 to 49 p40 to p47 l n-ch medium-voltage open-drain output-only ports 64 66 p50/da1 k n-ch open-drain i/o port also serves as a d/a channel 1 output. this port is a hysteresis input type. 63 65 p51/da2 k n-ch open-drain i/o port also serves as a d/a channel 2 output. this port is a hysteresis input type. 62 64 p52/pwm h n-ch open-drain i/o port also serves as the pwm output by the two pwm timers. this port is a hysteresis input type. 61 63 p53/pto2 h n-ch open-drain i/o port also serves as the toggle output for the 2-channel pwm timer. this port is a hysteresis input type. 60 62 p54/bz h n-ch open-drain i/o port also serves as a buzzer output. this port is a hysteresis input type. 59 61 p55/sck2 h n-ch open-drain i/o port also serves as the clock i/o for the serial i/o 2. this port is a hysteresis input type. 58 60 p56/so2 h n-ch open-drain i/o port also serves as the data output for the serial i/o 2. this port is a hysteresis input type. 57 59 p57/si2 h n-ch open-drain i/o port also serves as the data input for the serial i/o 2. this port is a hysteresis input type. 77 to 70 79 to 72 p60/an0 to p67/an7 i n-ch open-drain output-only ports also serve as the analog input for the a/d converter. these ports are a hysteresis input type. 2, 1, 80 to 78 4 to 1, 80 p70/li0 to p74/li4 j input-only ports also serve as external interrupt 1 input. these ports are a hysteresis input type.
10 mb89640 series (continued) *1: fpt-80p-m11 *2: fpt-80p-m06 *3: mqp-80c-p01 pin no. pin name circuit type function qfp *1 qfp *2 mqfp *3 7 9 x0a b subclock oscillator pins (32.768 khz) 810x1a 53 55 v cc ? power supply pin 13, 56 15, 58 v ss ? power supply (gnd) pin 66 68 av cc ? a/d converter power supply pin use this pin at the same voltage as v cc . 67, 68 69, 70 avrh, avrl ? a/d converter reference voltage input pins 65 67 davc ? d/a converter power supply pin use this pin at the same voltage as v cc . 69 71 av ss ? analog circuit power supply pin use this pin at the same voltage as v ss . 3 to 6 5 to 8 p83/int3 to p80/int0 j input-only ports also serve as an external interrupt 2 input. these ports are a hysteresis input type.
11 mb89640 series ? external eprom pins (mb89pv640 only) pin no. pin name i/o function 82 v pp o h level output pin 83 84 85 86 87 88 89 90 91 a12 a7 a6 a5 a4 a3 a2 a1 a0 o address output pins 93 94 95 o1 o2 o3 i data input pins 96 v ss o power supply (gnd) pin 98 99 100 101 102 o4 o5 o6 o7 o8 i data input pins 103 ce o rom chip enable pin outputs h during standby. 104 a10 o address output pin 105 oe o rom output enable pin outputs l at all times. 107 108 109 a11 a9 a8 o address output pins 110 a13 o 111 a14 o 112 v cc o eprom power supply pin 81 92 97 106 n.c. internally connected pins be sure to leave them open.
12 mb89640 series n i/o circuit type (continued) type circuit remarks a main clock ? at an oscillation feedback resistor of approximately 1 m w /5.0 v b subclock ? at an oscillation feedback resistor of approximately 4.5 m w /5.0 v c d ? at an output pull-up resistor (p-ch) of approximately 50 k w /5.0 v ? hysteresis input e ? cmos output ? cmos input ? pull-up resistor optional x1 x0 standby control signal x1a x0a standby control signal r p-ch n-ch p-ch n-ch r p-ch
13 mb89640 series (continued) (continued) type circuit remarks f ? cmos output ? hysteresis input ? pull-up resistor optional g ? cmos output ? pull-up resistor optional h ? n-ch open-drain output ? hysteresis input ? pull-up resistor optional i ? n-ch open-drain output ? analog input ? pull-up resistor optional j ? hysteresis input ? pull-up resistor optional p-ch n-ch p-ch r p-ch n-ch r p-ch n-ch p-ch r n-ch p-ch analog input p-ch r r
14 mb89640 series (continued) type circuit remarks k ? n-ch open-drain output ? hysteresis input ? analog output ? pull-up resistor optional l ? n-ch open-drain output ? medium voltage ? pull-up resistor optional enable analog output n-ch p-ch p-ch r n-ch p-ch r
15 mb89640 series n handling devices 1. preventing latchup latchup may occur on cmos ics if voltage higher than v cc or lower than v ss is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on 1. absolute maximum ratings in section n electrical characteristics is applied between v cc and v ss . when latchup occurs, power supply current increases rapidly and might thermally damage elements. when using, take great care not to exceed the absolute maximum ratings. also, take care to prevent the analog power supply (av cc and avrh) and analog input from exceeding the digital power supply (v cc ) when the analog system power supply is turned on and off. 2. treatment of unused input pins leaving unused input pins open could cause malfunctions. they should be connected to a pull-up or pull-down resistor. 3. treatment of power supply pins on microcontrollers with a/d and d/a converters connect to be av cc = davc = v cc and av ss = avrh = v ss even if the a/d and d/a converters are not in use. 4. treatment of n.c. pins be sure to leave (internally connected) n.c. pins open. 5. power supply voltage fluctuations although v cc power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. stabilizing voltage supplied to the ic is therefore important. as stabilization guidelines, it is recommended to control power so that v cc ripple fluctuations (p-p value) will be less than 10% of the standard v cc value at the commercial frequency (50 to 60 hz) and the transient fluctuation rate will be less than 0.1 v/ms at the time of a momentary fluctuation such as when power is switched. 6. precautions when using an external clock even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and wake-up from stop mode.
16 mb89640 series n programming to the eprom on the MB89P647 the MB89P647 is an otprom version of the mb89640 series. 1. features ? 32-kbyte prom on chip ? options can be set using the eprom programmer. ? equivalency to the mbm27c256a in eprom mode (when programmed with the eprom programmer) 2. memory space memory space in each mode such as 32-kbyte prom, option area is diagrammed below. ? precautions (1) the program area of the MB89P647 is 7 bytes smaller than that of the mb89pv640 and mb89647 to provide an option area. note this point during program development. (2) during normal operation, the option data is read when the option area is read from the cpu. 3. programming to the eprom in eprom mode, the MB89P647 functions equivalent to the mbm27c256a. this allows the prom to be programmed with a general-purpose eprom programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. ? programming procedure (1) set the eprom programmer to the mbm27c256a. (2) load program data into the eprom programmer at 0007 h to 7fff h (note that addresses 8007 h to ffff h while operating as internal rom mode assign to 0007 h to 7fff h in eprom mode). load option data into addresses 0000 h to 0006 h of the eprom programmer. (for information about each corresponding option, see 7. setting otprom options.) (3) program with the eprom programmer. 0000 h 0080 h 0180 h 8000 h ffff h i/o ram not available prom 32 kb 0000 h 7fff h eprom 32 kb option area single chip address eprom mode (corresponding addresses on the eprom programmer) 8007 h 0007 h not available
17 mb89640 series 4. recommended screening conditions high-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked otprom microcomputer program. 5. programming yield all bits cannot be programmed at fujitsu shipping test to a blanked otprom microcomputer, due to its nature. for this reason, a programming yield of 100% cannot be assured at all times. 6. eprom programmer socket adapter inquiry: sun hayato co., ltd.: tel 81-3-3802-5760 note: depending on the eprom programmer, inserting a capacitor of about 0.1 m f between v pp and v ss or v cc and v ss can stabilize programming operations. package compatible socket adapter fpt-80p-m06 rom-80qf-28dp-8l2 fpt-80p-m11 rom-80qf2-28dp-8l program, verify aging +150?, 48 hrs. data verification assembly
18 mb89640 series 7. setting otprom options the programming procedure is the same as that for the prom. options can be set by programming values at the addresses shown on the memory map. the relationship between bits and options is shown on the following bit map: ? otprom option bit map notes: set each bit to 1 to erase. do not write 0 to the vacant bit. the read value of the vacant bit is 1, unless 0 is written to it. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0000 h vacancy readable and writable vacancy readable and writable vacancy readable and writable single/dual- clock system 1: dual clock 2: single clock reset pin output 1: yes 2: no power-on reset 1: yes 2: no oscillation stabilization time 00: 2 4 /f ch 01: 2 17 /f ch 10: 2 14 /f ch 11: 2 18 /f ch 0001 h p07 pull-up 1: no 0: yes p06 pull-up 1: no 0: yes p05 pull-up 1: no 0: yes p04 pull-up 1: no 0: yes p03 pull-up 1: no 0: yes p02 pull-up 1: no 0: yes p01 pull-up 1: no 0: yes p00 pull-up 1: no 0: yes 0002 h p17 pull-up 1: no 0: yes p16 pull-up 1: no 0: yes p15 pull-up 1: no 0: yes p14 pull-up 1: no 0: yes p13 pull-up 1: no 0: yes p12 pull-up 1: no 0: yes p11 pull-up 1: no 0: yes p10 pull-up 1: no 0: yes 0003 h p37 pull-up 1: no 0: yes p36 pull-up 1: no 0: yes p35 pull-up 1: no 0: yes p34 pull-up 1: no 0: yes p33 pull-up 1: no 0: yes p32 pull-up 1: no 0: yes p31 pull-up 1: no 0: yes p30 pull-up 1: no 0: yes 0004 h p67 pull-up 1: no 0: yes p66 pull-up 1: no 0: yes p65 pull-up 1: no 0: yes p64 pull-up 1: no 0: yes p63 pull-up 1: no 0: yes p62 pull-up 1: no 0: yes p61 pull-up 1: no 0: yes p60 pull-up 1: no 0: yes 0005 h vacancy readable and writable vacancy readable and writable vacancy readable and writable p74 pull-up 1: no 0: yes p73 pull-up 1: no 0: yes p72 pull-up 1: no 0: yes p71 pull-up 1: no 0: yes p70 pull-up 1: no 0: yes 0006 h vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable p83 pull-up 1: no 0: yes p82 pull-up 1: no 0: yes p81 pull-up 1: no 0: yes p80 pull-up 1: no 0: yes
19 mb89640 series n programming to the eprom with piggyback/evaluation device 1. eprom for use mbm27c256a-20tv 2. programming socket adapter to program to the prom using an eprom programmer, use the socket adapter (manufacturer: sun hayato co., ltd.) listed below. inquiry: sun hayato co., ltd.: tel 81-3-3802-5760 3. memory space memory space in each mode, such as 32-kbyte prom is diagrammed below. 4. programming to the eprom (1) set the eprom programmer to the mbm27c256a. (2) load program data into the eprom programmer at 0007 h to 7fff h . (3) program to 0000 h to 7fff h with the eprom programmer. package adapter socket part number lcc-32 (rectangle) rom-32lc-28dp-yg prom 32 kb ffff h 0000 h 8000 h 0080 h 0480 h not available single chip i/o ram 8007 h not available 7fff h 0000 h 0007 h eprom 32 kb not available corresponding addresses on the eprom programmer address
20 mb89640 series n block diagram clock controller reset circuit time-base timer main clock oscillator subclock oscillator (32.768 khz) watch prescaler cmos i/o ports cmos output port port 2 port 0 and port 1 external bus interface f 2 mc-8l cpu ram v cc , v ss other pins x0 x1 x0a x1a rst 8 8 p00/ad0 to p07/ad7 p10/a08 to p17/a15 mod0 mod1 p27/ale p26/rd p25/wr p24/clk p23/rdy p22/hrq p21/hak p20/bufc rom cmos i/o port port 3 port 5 8-bit pulse width counter 16-bit timer/counter serial i/o 1 2-channel 8-bit pwm timer serial i/o 2 buzzer output 2-channel 8-bit d/a converter n-ch open-drain i/o port port 4 medium-voltage n-ch open-drain output port n-ch open-drain output port 8-bit a/d converter cmos input port cmos input port external interrupt 1 external interrupt 2 8 5 4 p67/an7 p66/an6 p65/an5 p64/an4 p63/an3 p62/an2 p61/an1 p60/an0 avrh avrl av cc av ss p74/li4 p73/li3 p72/li2 p71/li1 p70/li0 p83/int3 p82/int2 p81/int1 p80/int0 p36/wto p35/pwc p34/ec p33/si1 p32/so1 p31/sck1 p30/adst p37/pto1 p57/si2 p56/so2 p55/sck2 p52/pwm p53/pto2 p54/bz p51/da2 p50/da1 davc p40 to p47 internal bus port 6 port 7 port 8
21 mb89640 series n cpu core 1. memory space the microcontrollers of the mb89640 series offer a memory space of 64 kbytes for storing all of i/o, data, and program areas. the i/o area is located at the lowest address. the data area is provided immediately above the i/o area. the data area can be divided into register, stack, and direct areas according to the application. the program area is located at exactly the opposite end, that is, near the highest address. provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. the memory space of the mb89640 series is structured as illustrated below. memory space note: since addresses 8000 h to 8006 h for the MB89P647 comprise an option area, do not use this area for the mb89pv640 and mb89647. 0000 h 0080 h 0100 h 0200 h 0480 h 8000 h 8007 h mb89pv640 i/o ram 1 kb register external area not available external rom 32 kb 0000 h 0080 h 0100 h 0180 h e000 h ffff h mb89643 i/o ram 256 b register external area not available rom 8 kb 0000 h 0080 h 0100 h 0200 h c000 h ffff h mb89645 i/o ram 512 b register external area rom 16 kb 0000 h 0080 h 0100 h 0200 h a000 h ffff h mb89646 i/o ram 768 b register external area rom 24 kb 0000 h 0080 h 0100 h 0200 h 0480 h 8000 h 8007 h ffff h MB89P647 mb89647 i/o ram 1 kb register external area not available 0280 h c000 h not available 0280 h 0380 h rom 32 kb ffff h
22 mb89640 series 2. registers the f 2 mc-8l family has two types of registers; dedicated registers in the cpu and general-purpose registers in the memory. the following dedicated registers are provided: program counter (pc): a 16-bit register for indicating instruction storage positions accumulator (a): a 16-bit temporary register for storing arithmetic operations, etc. when the instruction is an 8-bit data processing instruction, the lower byte is used. temporary accumulator (t): a 16-bit register which performs arithmetic operations with the accumulator when the instruction is an 8-bit data processing instruction, the lower byte is used. index register (ix): a 16-bit register for index modification extra pointer (ep): a 16-bit pointer for indicating a memory address stack pointer (sp): a 16-bit register for indicating a stack area program status (ps): a 16-bit register for storing a register pointer, a condition code the ps can further be divided into higher 8 bits for use as a register bank pointer (rp) and the lower 8 bits for use as a condition code register (ccr). (see the diagram below.) pc a t ix ep sp ps 16 bits : program counter : accumulator : temporary accumulator : index register : extra pointer : stack pointer : program status fffd h undefined undefined undefined undefined undefined i-flag = 0, il1, 0 = 11 other bits are undefined. initial value structure of the program status register vacancy h i il1, 0 n z vc 54 rp ps 109876 3210 15 14 13 12 11 rp ccr vacancy vacancy
23 mb89640 series the rp indicates the address of the register bank currently in use. the relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. the ccr consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of cpu operations at the time of an interrupt. h-flag: set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. cleared otherwise. this flag is for decimal adjustment instructions. i-flag: interrupt is allowed when this flag is set to 1. interrupt is prohibited when the flag is set to 0. set to 0 when reset. il1, 0: indicates the level of the interrupt currently allowed. processes an interrupt only if its request level is higher than the value indicated by this bit. n-flag: set if the msb is set to 1 as the result of an arithmetic operation. cleared when the bit is set to 0. z-flag: set when an arithmetic operation results in 0. cleared otherwise. v-flag: set if the complement on 2 overflows as a result of an arithmetic operation. reset if the overflow does not occur. c-flag: set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. cleared otherwise. set to the shift-out value in the case of a shift instruction. il1 il0 interrupt level high-low 00 1 high low = no interrupt 01 10 2 11 3 rule for conversion of actual addresses of the general-purpose register area ? a15 ? a14 ? a13 ? a12 ? a11 ? a10 ? a9 ? a8 r4 a7 r3 a6 r2 a5 r1 a4 r0 a3 b2 a2 b1 a1 b0 a0 rp generated addresses lower op codes
24 mb89640 series the following general-purpose registers are provided: general-purpose registers: an 8-bit register for storing data the general-purpose registers are 8 bits and located in the register banks of the memory. one bank contains eight registers. up to a total of 16 banks can be used on the mb89643 and a total of 32 banks can be used on the mb89645/646/647/p647/pv640. the bank currently in use is indicated by the register bank pointer (rp). note: the number of register banks that can be used varies with the ram size. register bank configuration this address = 0100 h + 8 (rp) memory area 32 banks r0 r1 r2 r3 r4 r5 r6 r7
25 mb89640 series n i/o map (continued) address read/write register name register description 00 h (r/w) pdr0 port 0 data register 01 h (w) ddr0 port 0 data direction register 02 h (r/w) pdr1 port 1 data register 03 h (w) ddr1 port 1 data direction register 04 h (r/w) pdr2 port 2 data register 05 h (w) bctr external bus control register 06 h vacancy 07 h (r/w) sycc system clock control register 08 h (r/w) stbc standby control register 09 h (r/w) wdtc watchdog timer control register 0a h (r/w) tbcr time-base timer control register 0b h (r/w) wpcr watch prescaler control register 0c h (r/w) pdr3 port 3 data register 0d h (w) ddr3 port 3 data direction register 0e h (r/w) pdr4 port 4 data register 0f h (r/w) buzr buzzer register 10 h (r/w) pdr5 port 5 data register 11 h (r/w) pdr6 port 6 data register 12 h (r) pdr7 port 7 data register 13 h (r) pdr8 port 8 data register 14 h vacancy 15 h vacancy 16 h vacancy 17 h vacancy 18 h (r/w) tmcr 16-bit timer control register 19 h (r/w) tchr 16-bit timer count register (h) 1a h (r/w) tclr 16-bit timer count register (l) 1b h vacancy 1c h (r/w) smr1 serial 1 mode register 1d h (r/w) sdr1 serial 1 data register 1e h (r/w) smr2 serial 2 mode register 1f h (r/w) sdr2 serial 2 data register
26 mb89640 series (continued) note: do not use vacancies. address read/write register name register description 20 h (r/w) adc1 a/d converter control register 1 21 h (r/w) adc2 a/d converter control register 2 22 h (r/w) adcd a/d converter data register 23 h vacancy 24 h (r/w) dacr d/a converter control register 25 h (w) dadr1 d/a converter data register 1 26 h (w) dadr2 d/a converter data register 2 27 h vacancy 28 h (r/w) cntr1 pwm timer control register 1 29 h (r/w) cntr2 pwm timer control register 2 2a h (r/w) cntr3 pwm timer control register 3 2b h (w) comr1 pwm timer compare register 1 2c h (w) comr2 pwm timer compare register 2 2d h (r/w) pcr1 pwc pulse width control register 1 2e h (r/w) pcr2 pwc pulse width control register 2 2f h (r/w) rlbr pwc reload buffer register 30 h vacancy 31 h (r/w) eic1 external interrupt 1 control register 1 32 h (r/w) eic2 external interrupt 1 control register 2 33 h (r/w) eie2 external interrupt 2 enable register 34 h (r/w) eif2 external interrupt 2 flag register 35 h to 7a h vacancy 7b h vacancy 7c h (w) ilr1 interrupt level setting register 1 7d h (w) ilr2 interrupt level setting register 2 7e h (w) ilr3 interrupt level setting register 3 7f h vacancy
27 mb89640 series n electrical characteristics 1. absolute maximum ratings (av ss = v ss = 0.0 v) (continued) parameter symbol value unit remarks min. max. power supply voltage v cc av cc davc v ss C 0.3 v ss + 7.0 v * a/d converter reference input voltage avrh v ss C 0.3 v ss + 7.0 v avrh must not exceed av cc + 0.3 v. avrl v ss C 0.3 v ss + 7.0 v avrl must not exceed avrh. program voltage v pp v ss C 0.3 13.0 v mod1 pin on MB89P647 input voltage v i v ss C 0.3 v cc + 0.3 v p52 to p57 with a pull-up resistor and other input ports v i2 v ss C 0.3 v ss + 7.0 v p52 to p57 without a pull-up resistor output voltage v o v ss C 0.3 v cc + 0.3 v p40 to p47 and p52 to p57 with a pull-up resistor and other output ports v o2 v ss C 0.3 v ss + 17.0 v p40 to p47 without a pull-up resistor v o3 v ss C 0.3 v ss + 7.0 v p52 to p57 without a pull-up resistor l level maximum output current i ol ? 20 ma l level average output current i olav ? 4ma average value (operating current operating rate) l level total average output current ? i olav ? 40 ma average value (operating current operating rate) l level total maximum output current ? i ol ? 100 ma h level maximum output current i oh ? C20 ma h level average output current i ohav ? C4 ma average value (operating current operating rate) h level total average output current ? i ohav ? C20 ma average value (operating current operating rate) h level total maximum output current ? i oh ? C50 ma power consumption p d ? 500 mw
28 mb89640 series (continued) (av ss = v ss = 0.0 v) * : use davc and av cc and v cc set at the same voltage. take care so that davc and av cc does not exceed v cc , such as when power is turned on. precautions: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. recommended operating conditions (av ss = v ss = 0.0 v) * : these values vary with the operating frequency and analog assurance range. see figure 1, 5. a/d converter electrical characteristics, and 6. d/a converter electrical characteristics. parameter symbol value unit remarks min. max. operating temperature t a C40 +85 c storage temperature tstg C55 +150 c parameter symbol value unit remarks min. max. power supply voltage v cc av cc davc 2.2* 6.0* v normal operation assurance range* (mb89643/645/646/647) 2.7* 6.0* v normal operation assurance range* (MB89P647/pv640) 1.5 6.0 v retains the ram state in stop mode a/d converter reference input voltage avrh 3.0 av cc v avrl 0.0 2.0 v operating temperature t a C40 +85 c
29 mb89640 series figure 1 operating voltage vs. main clock operating frequency figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/f ch . since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the operating speed is switched using a gear. 1 2 3 4 5 6 1.0 10.0 operation assurance range operating voltage (v) 5.0 4.0 0.4 0.8 2.0 minimum execution time (instruction cycle) (?) analog accuracy assured in the v cc = av cc = davc = 3.5 v to 6.0 v range. 1.0 0.5 main clock operating frequency (at an instruction cycle of 4/f ch ) (mhz) note: the shaded area is assured only for the mb89643/645/646/647.
30 mb89640 series 3. dc characteristics (av cc = davc = v cc = +5.0 v, av ss = v ss = 0.0 v, f ch = 10 mhz, f cl = 32.768 khz, t a = C40 c to +85 c) (continued) parameter symbol pin condition value unit remarks min. typ. max. h level input voltage *1 v ih p00 to p07, p10 to p17, p22, p23 ? 0.7 v cc ? v cc + 0.3 v v ihs rst , p30 to p37, p50, p51, p70 to p74, p80 to p83 0.8 v cc ? v cc + 0.3 v p52 to p57 with pull-up resistor v ihs2 p52 to p57 0.8 v cc ? v ss + 6.0 v without pull- up resistor l level input voltage *1 v il p00 to p07, p10 to p17, p22, p23 v ss - 0.3 ? 0.3 v cc v v ils rst , p30 to p37, p50 to p57, p70 to p74, p80 to p83 v ss - 0.3 ? 0.2 v cc v open-drain output pin application voltage v d p40 to p47 v ss - 0.3 ? v ss + 15.0 v without pull- up resistor v d2 p52 to p57 v ss - 0.3 ? v ss + 6.0 v without pull- up resistor v d3 p60 to p67 v ss - 0.3 ? v cc + 0.3 v p40 to p47, p52 to p57 with pull-up resistor h level output voltage v oh p00 to p07, p10 to p17, p20 to p27, p30 to p37 i oh = C2.0 ma 2.4 ?? v l level output voltage v ol p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p50 to p57, p60 to p67 i ol = +1.8 ma ?? 0.4 v v ol2 rst i ol = +4.0 ma ?? 0.4 v input leakage current (hi-z output leakage current) i li1 p00 to p07, p10 to p17, p20 to p27, p30 to p37, p50 to p57, p70 to p74, p80 to p83, mod0, mod1 0.45 v < v i < v cc ?? 5 m a without pull- up resistor
31 mb89640 series (av cc = davc = v cc = +5.0 v, av ss = v ss = 0.0 v, f ch = 10 mhz, f cl = 32.768 khz, t a = C40 c to +85 c) *1: connect mod0 and mod1 to v cc or v ss . *2: high-speed operation is the operation when the system clock is set to the maximum speed by the system clock select bit at 10-mhz clock. *3: low-speed operation is the operation when the system clock is set to the maximum speed by the system clock select bit at 10-mhz clock. parameter symbol pin condition value unit remarks min. typ. max. pull-up resistance r pull p00 to p07, p10 to p17, p30 to p37, p40 to p47, p50 to p57, p60 to p64, p70 to p74, p80 to p83, rst v i = 0.0 v 25 50 100 k w without pull- up resistor power supply current i cc1 v cc v cc = +5.0 v ? main clock operation ? high speed *2 10 20ma 11 23ma MB89P647 only i cc2 v cc = +3.0 v ? main clock operation ? low speed *3 1.5 2ma 2.5 5ma MB89P647 only i cs1 v cc = +5.0 v ? main clock sleep ? high speed *2 3 7ma i cs2 v cc = +3.0 v ? main clock sleep ? low speed *3 11.5ma i cs3 v cc = +3.0 v subclock sleep 25 50 m a i cch t a = +25 c subclock stop 10 m a i csb v cc = +3.0 v subclock operation (32.768 khz) 50100 m a 1 3ma MB89P647 only power supply current i cct v cc v cc = +3.0 v watch mode (32.768 khz) 15 m a i a av cc ? main clock operation ? high speed *2 1 3ma input capacitance c in other than av cc , av ss , v cc , and v ss f = 1 mhz 10 ? pf
32 mb89640 series 4. ac characteristics (1) reset timing (v cc = +5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : t xcyl is the oscillation cycle (1/f ch ) to input to the x0 pin. (2) power-on reset (av ss = v ss = 0.0 v, t a = C40 c to +85 c) note: make sure that power supply rises within the selected oscillation stabilization time. for example, when the main clock is operating at 10 mhz (f ch ) and the oscillation stabilization time select option has been set to 2 14 /f ch , the oscillation stabilization delay time is 1.6 ms and accordingly the maximum value of power supply rising time is about 1.6 ms. keep in mind that abrupt changes in power supply voltage may cause a power-on reset. if power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. parameter symbol condition value unit remarks min. max. rst l pulse width t zlzh 48 t xcyl ns parameter symbol condition value unit remarks min. max. power supply rising time t r 50ms power supply cut-off time t off 1 ms due to repeated operation 0.2 v cc 0.2 v cc rst t zlzh 0.2 v 0.2 v 2.0 v v cc 0.2 v t r t off
33 mb89640 series (3) clock timing (av ss = v ss = 0.0 v, t a = C40 c to +85 c) parameter symbol pin condition value unit remarks min. typ. max. clock frequency f ch x0, x1 110mhz f cl x0a, x1a 32.768 khz clock cycle time t xcyl x0, x1 100 1000 ns t lxcyl x0a, x1a 30.5 m s input clock pulse width p wh p wl x0 20 ns external clock p whl p wll x0a 30.5 m s input clock rising/falling time t cr t cf x0 10 ns external clock 0.2 v cc 0.8 v cc x0 0.2 v cc t cr t cf 0.8 v cc 0.2 v cc x0 x1 x0 x1 when a crystal or ceramic resonator is used. when an external clock is used. open t xcyl p wl p wh x0 and x1 timing and conditions main clock conditions
34 mb89640 series (4) instruction cycle parameter symbol value (typical) unit remarks instruction cycle (minimum execution time) t inst 4/f ch system clock selection 11 m s t inst = 0.4 m s when operating at f ch = 10 mhz 8/f ch system clock selection 10 m s t inst = 0.8 m s when operating at f ch = 10 mhz 16/f ch system clock selection 01 m s t inst = 1.6 m s when operating at f ch = 10 mhz 64/f ch system clock selection 00 m s t inst = 6.4 m s when operating at f ch = 10 mhz when an external clock is used. 0.2 v cc 0.8 v cc x0a 0.2 v cc t cr t cf 0.8 v cc 0.2 v cc x0a x1a x0a x1a open t lxcyl p whl p wll when a crystal or ceramic resonator is used. x0a and x1a timing and conditions subclock conditions
35 mb89640 series (5) recommended resonator manufacturers inquiry: fujitsu limited far part number (built-in capacitor type) frequency initial deviation of far frequency (t a = +25c) temperature characteristic of far frequency (t a = C20c to +60c) far-c4cb-08000-m02 8.00 mhz 0.5% 0.5% far-c4cb-10000-m02 10.00 mhz 0.5% 0.5% sample application of piezoelectric resonator (far series) x0 x1 far * c1 c2 * : fujitsu acoustic resonator c1 = c2 = 20 pf? pf (built-in far)
36 mb89640 series inquiry: kyocera corporation ? avx corporation north american sales headquarters: tel 1-803-448-9411 ? avx limited european sales headquarters: tel 44-1252-770000 ? avx/kyocera h.k. ltd. asian sales headquarters: tel 852-363-3303 murata mfg. co., ltd. ? murata electronics north america, inc.: tel 1-404-436-1300 ? murata europe management gmbh: tel 49-911-66870 ? murata electronics singapore (pte.) ltd.: tel 65-758-4233 (6) clock output timing (v cc = +5.0 v10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) resonator manufacturer* resonator frequency c1 (pf) c2 (pf) r (k w ) kyocera corporation kbr-7.68mws 7.68 mhz 33 33 ? kbr-8.0mws 8.0 mhz 33 33 ? murata mfg. co., ltd. csa8.00mtz 8.0 mhz 30 30 ? parameter symbol pin condition value unit remarks min. max. cycle time t cyc clk 200 ns t xcyl 2 at 10 mhz oscillation clk -? clk t chcl clk 30 100 ns approx. t cyl /2 at 10 mhz oscillation sample application of ceramic resonator x1 c1 c2 x0 * 2.4 v clk 0.8 v 2.4 v t cyc t chcl
37 mb89640 series (7) bus read timing (v cc = +5.0 v10%, f ch = 10 mhz, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst , see (4) instruction cycle. parameter symbol pin condition value unit remarks min. max. valid address ? rd time t avrl rd , a15 to 08, ad7 to 0 1/4 t inst * C 64 ns ns rd pulse width t rlrh rd 1/2 t inst * C 20 ns ns valid address ? read data time t avdv ad7 to 0, a15 to 08 1/2 t inst * 200 ns no wait rd ? read data time t rldv rd , ad7 to 0 1/2 t inst * C 80 ns 120 ns no wait rd - ? data hold time t rhdx ad7 to 0, rd 0ns rd - ? ale - time t rhlh rd , ale 1/4 t inst * C 40 ns ns rd - ? address invalid time t rhax rd , a15 to 08 1/4 t inst * C 40 ns ns rd ? clk - time t rlch rd , clk 1/4 t inst * C 40 ns ns clk ? rd - time t clrh rd , clk 0 ns rd ? bufc time t rlbl rd , bufc C5 ns bufc -? valid address time t bhav a15 to 08, ad7 to 0, bufc 5ns ale ad a rd bufc clk 2.4 v 0.8 v 0.8 v 2.4 v 0.8 v 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc 2.4 v 0.8 v 2.4 v 0.8 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 2.4 v 0.8 v t rhdx t bhav t avdv t rlbl t clrh t rhlh t avrl t rlch t rldv t rlrh t rhax
38 mb89640 series (8) bus write timing (v cc = +5.0 v10%, f ch = 10 mhz, av ss = v ss = 0.0 v, t a = C40 c to +85 c) *1: for information on t inst , see (4) instruction cycle. *2: these characteristics are also applicable to the bus read timing. parameter symbol pin condition value unit remarks min. max. valid address ? ale time t avll ad7 to 0, ale, a15 to 08 1/4 t inst *1 C 64 ns *2 ns ale ? address invalid time t llax ad7 to 0, ale, a15 to 08 5ns*2 valid address ? wr time t avwl wr , ale 1/4 t inst *1 C 60 ns ns wr pulse width t wlwh wr 1/2 t inst *1 C 20 ns ns write data ? wr - time t dvwh ad7 to 0, wr 1/2 t inst *1 C 60 ns ns wr - ? address invalid time t whax wr , a15 to 08 1/4 t inst *1 C 40 ns ns wr - ? data hold time t whdx ad7 to 0, wr 1/4 t inst *1 C 40 ns ns wr - ? ale - time t whlh wr , ale 1/4 t inst *1 C 40 ns ns wr ? clk - time t wlch wr , clk 1/4 t inst *1 C 40 ns ns clk ? wr - time t clwh wr , clk 0 ns ale pulse width t lhll ale 1/4 t inst *1 C 35 ns *2 ns ale ? clk - time t llch ale, clk 1/4 t inst *1 C 30 ns *2 ns ale ad a wr clk 2.4 v 0.8 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v t avwl 2.4 v 0.8 v t clwh 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v t llax t whlh t llch t lhll t avll t dvwh t whdx t whax t wlwh t wlch
39 mb89640 series (9) ready input timing (v cc = +5.0 v10%, f ch = 10 mhz, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : these characteristics are also applicable to the read cycle. parameter symbol pin condition value unit remarks min. max. rdy valid ? clk - time t yvch rdy, clk 60 ns * clk - ? rdy invalid time t chyx rdy, clk 0 ns * clk ale ad a wr rdy address t yvch t chyx t yvch t chyx 2.4 v 2.4 v note: the bus cycle is also extended in the read cycle in the same manner. data
40 mb89640 series (10) serial i/o timing (v cc = +5.0 v10%, f ch = 10 mhz, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst , see (4) instruction cycle. parameter symbol pin condition value unit remarks min. max. serial clock cycle time t scyc sck1, sck2 internal shift clock mode 2 t inst * m s sck1 ? so1 time sck2 ? so2 time t slov sck1, so1 sck2, so2 C200 200 ns valid si1 ? sck1 - valid si2 ? sck2 - t ivsh si1, sck1 si2, sck2 1/2 t inst * m s sck1 - ? valid si1 hold time sck2 - ? valid si2 hold time t shix sck1, si1 sck2, si2 1/2 t inst * m s serial clock h pulse width t shsl sck1, sck2 external shift clock mode 1 t inst * m s serial clock l pulse width t slsh sck1, sck2 1 t inst * m s sck1 ? so1 time sck2 ? so2 time t slov sck1, so1 sck2, so2 0 200 ns valid si1 ? sck1 - valid si2 ? sck2 - t ivsh si1, sck1 si2, sck2 1/2 t inst * m s sck1 - ? valid si1 hold time sck2 - ? valid si2 hold time t shix sck1, si1 sck2, si2 1/2 t inst * m s
41 mb89640 series t slsh 2.4 v t slov 0.2 v cc t shix 0.8 v cc 0.8 v t ivsh 0.8 v cc 0.2 v cc 0.8 v cc sck1 so1 si1 sck2 so2 si2 t shsl 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v 2.4 v t scyc 2.4 v t slov 0.2 v cc t shix 0.8 v 0.8 v t ivsh 0.8 v cc 0.2 v cc 0.8 v cc sck1 so1 si1 sck2 so2 si2 internal shift clock mode external shift clock mode
42 mb89640 series (11) peripheral input timing (v cc = +5.0 v10%, f ch = 10 mhz, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst, see (4) instruction cycle. parameter symbol pin condition value unit remarks min. max. peripheral input pulse h width 1 t ilih1 pwc, ec, int0 to int3 2 t inst * m s peripheral input pulse l width 1 t ihil1 pwc, ec, int0 to int3 2 t inst * m s peripheral input pulse h width 2 t ilih2 adst a/d mode 32 t inst * m s peripheral input pulse l width 2 t ihil2 adst 32 t inst * m s peripheral input pulse h width 2 t ilih2 adst sense mode 8 t inst * m s peripheral input pulse l width 2 t ihil2 adst 8 t inst * m s 0.2 v cc 0.8 v cc t ihil1 0.8 v cc pwc ec int0 to 3 0.2 v cc t ilih1 0.2 v cc 0.8 v cc t ihil2 0.8 v cc adst 0.2 v cc t ilih2
43 mb89640 series 5. a/d converter electrical characteristics (av cc = v cc = +3.5 v to +6.0 v, f ch = 10 mhz, av ss = v ss = avrl = 0.0 v, t a = C40 c to +85 c) * : for information on t inst , see (4) instruction cycle. parameter symbol pin condition value unit remarks min. typ. max. resolution 8bit total error avrh = av cc 3.0 lsb linearity error 1.0 lsb differential linearity error 0.9 lsb zero transition voltage v ot C1.0 +0.5 +2.0 lsb full-scale transition voltage v fst avrh C 4.5 avrh C 1.5 avrh + 1.5 lsb interchannel disparity 0.5lsb a/d mode conversion time 44t inst * sense mode conversion time 12t inst * analog port input current i ain an0 to an7 10 m a analog input voltage 0 avrh v reference voltage avrh 0av cc v reference voltage supply current i r when a/d conversion is activated avrh = 5.0 v 100 ?m a i rh when a/d conversion is stopped avrh = 5.0 v 1 m a
44 mb89640 series (1) a/d glossary ? resolution analog changes that are identifiable with the a/d converter. when the number of bits is 8, analog voltage can be divided into 2 8 = 256. ? linearity error (unit: lsb) the deviation of the straight line connecting the zero transition point (0000 0000 ? 0000 0001) with the full-scale transition point (1111 1111 ? 1111 1110) from actual conversion characteristics ? differential linearity error (unit: lsb) the deviation of input voltage needed to change the output code by 1 lsb from the theoretical value ? total error (unit: lsb) the difference between theoretical and actual conversion values (2) precautions ? input impedance of the analog input pins the a/d converter used for the mb89640 series contains a sample hold circuit as illustrated below to fetch analog input voltage into the sample hold capacitor for eight instruction cycles after activating a/d conversion. for this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage might not stabilize within the analog input sampling period. therefore, it is recommended to keep the output impedance of the external circuit low (below 10 k w ). note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about 0.1 m f for the analog input pin. v ot v nt v (n + 1)t v fst digital output (1 lsb n + v ot ) 0000 0000 0000 0000 0001 0010 1111 1111 1110 1111 1 lsb = avrh ?avrl 256 linearity error = differential linearity error = analog input actual conversion value theoretical conversion value total error = v nt ?(1 lsb n + v ot ) 1 lsb v ( n + 1 ) t ?v nt 1 lsb ?1 1 lsb v nt ?(1 lsb n + 1 lsb) linearity error
45 mb89640 series ?error the smaller the | avrh C avrl |, the greater the error would become relatively. 6. d/a converter electrical characteristics (davc = v cc = +3.5 v to +6.0 v, f ch =10 mhz, av ss = v ss = 0.0 v, t a = C40 c to +85 c) parameter symbol value unit remarks min. typ. max. resolution 8bit linearity error 1.0 lsb davc = v cc = 5.0 v differential linearity error 0.9 lsb output impedance 20 k w d/a analog power supply current (for one channel) i dina 0.1 ? ma at no load and conversion cycle of 5 m s i dins 0.1 m a during power down sample hold circuit analog channel selector close for 8 instruction cycles after activating a/d conversion. if the analog input impedance is higher than 10 k w, it is recommended to contact an external capacitor of about 0.1 m f. analog input pin comparator r = 6 k w . . c = 33 pf . . analog input equivalent circuit
46 mb89640 series n examples characteristics 010 123456789 0 v ol (mv) 11 12 13 14 15 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 i ol (ma) v cc = 5 v t a = +25? v ol vs. i ol 010 123456789 0.1 0.2 0.3 0.4 0.5 0.6 v ol (v) v cc = 2.5 v v cc = 3.0 v v cc = 4.0 v v cc = 5.0 v v cc = 6.0 v i ol (ma) 0.0 v ol vs. i ol t a = +25? 0.0 1.0 v cc ? oh (v) v cc = 2.5 v v cc = 3.0 v v cc = 4.0 v v cc = 5.0 v v cc = 6.0 v i oh (ma) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 ?.5 ?.0 ?.5 ?.0 ?.5 ?.0 t a = +25? v cc ? oh vs. i oh (1) l level output voltage (p00 to p07, p10 to p17, p20 to p27, p30 to p37, p50 to p57, p60 to p67) (2) h level output voltage (p00 to p07, p10 to p17, p20 to p27, p30 to p37) (3) l level output voltage (p40 to p47) (4) h level input voltage/l level input voltage (cmos input) 012 3 456 7 v cc (v) 5.0 v in (v) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 v in vs. v cc t a = +25?
47 mb89640 series (5) h level input voltage/l level input voltage (hysteresis input) (6) power supply current (external clock) (continued) 012 3 456 7 v cc (v) 5.0 v in (v) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 v ihs v ils t a = +25? v in vs. v cc v ihs : threshold when input voltage in hysteresis characteristics is set to h level v ils : threshold when input voltage in hysteresis characteristics is set to l level 23 4 56 main clock operation mode (4/f ch instruction) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 i cc (ma) 15 8 mhz 6 mhz 4 mhz 2 mhz 1 mhz xtal 10 mhz v cc (v) i cc vs. v cc main clock operation mode (64/f ch instruction) i cc vs. v cc t a = +25? t a = +25? i cc (ma) 23 4 56 0 1 2 3 8 mhz 6 mhz 4 mhz 2 mhz 1 mhz xtal 10 mhz v cc (v)
48 mb89640 series (continued) (7) pull-up resistance 23 4 56 main clock sleep mode (4/f ch instruction) i cs1 (ma) 8 mhz 6 mhz 4 mhz 2 mhz 1 mhz xtal 10 mhz 0 2 3 1 4 v cc (v) i cs1 vs. v cc main clock sleep mode (64/f ch instruction) i cs2 vs. v cc t a = +25? 23 4 56 i cs2 ( m a) 8 mhz 6 mhz 4 mhz 2 mhz 1 mhz xtal 10 mhz 0 500 1,000 1,500 v cc (v) t a = +25? 23 4 56 subclock mode i cs3 ( m a) t a = +25? operation 120 sleep watch 0 20 40 60 80 100 v cc (v) i cs3 vs. v cc 234 5 6 r pull (k w ) 10 1 100 1000 v cc (v) r pull vs. v cc t a = +25?
49 mb89640 series n instructions execution instructions can be divided into the following four groups: ? transfer ? arithmetic operation ? branch ?others table 1 lists symbols used for notation of instructions. table 1 instruction symbols (continued) symbol meaning dir direct address (8 bits) off offset (8 bits) ext extended address (16 bits) #vct vector table number (3 bits) #d8 immediate data (8 bits) #d16 immediate data (16 bits) dir: b bit direct address (8:3 bits) rel branch relative address (8 bits) @ register indirect (example: @a, @ix, @ep) a accumulator a (whether its length is 8 or 16 bits is determined by the instruction in use.) ah upper 8 bits of accumulator a (8 bits) al lower 8 bits of accumulator a (8 bits) t temporary accumulator t (whether its length is 8 or 16 bits is determined by the instruction in use.) th upper 8 bits of temporary accumulator t (8 bits) tl lower 8 bits of temporary accumulator t (8 bits) ix index register ix (16 bits)
50 mb89640 series (continued) columns indicate the following: mnemonic: assembler notation of an instruction ~: number of instructions #: number of bytes operation: operation of an instruction tl, th, ah: a content change when each of the tl, th, and ah instructions is executed. symbols in the column indicate the following: ? C indicates no change. ? dh is the 8 upper bits of operation description data. ? al and ah must become the contents of al and ah immediately before the instruction is executed. ? 00 becomes 00. n, z, v, c: an instruction of which the corresponding flag will change. if + is written in this column, the relevant instruction will change its corresponding flag. op code: code of an instruction. if an instruction is more than one code, it is written according to the following rule: example: 48 to 4f ? this indicates 48, 49, ... 4f. symbol meaning ep extra pointer ep (16 bits) pc program counter pc (16 bits) sp stack pointer sp (16 bits) ps program status ps (16 bits) dr accumulator a or index register ix (16 bits) ccr condition code register ccr (8 bits) rp register bank pointer rp (5 bits) ri general-purpose register ri (8 bits, i = 0 to 7) indicates that the very is the immediate data. (whether its length is 8 or 16 bits is determined by the instruction in use.) ( ) indicates that the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.) (( )) the address indicated by the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.)
51 mb89640 series table 2 transfer instructions (48 instructions) notes: during byte transfer to a, t ? a is restricted to low bytes. operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (reverse arrangement of f 2 mc-8 family) mnemonic ~ # operation tl th ah n z v c op code mov dir,a mov @ix +off,a mov ext,a mov @ep,a mov ri,a mov a,#d8 mov a,dir mov a,@ix +off mov a,ext mov a,@a mov a,@ep mov a,ri mov dir,#d8 mov @ix +off,#d8 mov @ep,#d8 mov ri,#d8 movw dir,a movw @ix +off,a movw ext,a movw @ep,a movw ep,a movw a,#d16 movw a,dir movw a,@ix +off movw a,ext movw a,@a movw a,@ep movw a,ep movw ep,#d16 movw ix,a movw a,ix movw sp,a movw a,sp mov @a,t movw @a,t movw ix,#d16 movw a,ps movw ps,a movw sp,#d16 swap setb dir: b clrb dir: b xch a,t xchw a,t xchw a,ep xchw a,ix xchw a,sp movw a,pc 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 5 4 2 3 4 5 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 3 1 1 3 2 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 (dir) ? (a) ( (ix) +off ) ? (a) (ext) ? (a) ( (ep) ) ? (a) (ri) ? (a) (a) ? d8 (a) ? (dir) (a) ? ( (ix) +off) (a) ? (ext) (a) ? ( (a) ) (a) ? ( (ep) ) (a) ? (ri) (dir) ? d8 ( (ix) +off ) ? d8 ( (ep) ) ? d8 (ri) ? d8 (dir) ? (ah),(dir + 1) ? (al) ( (ix) +off) ? (ah), ( (ix) +off + 1) ? (al) (ext) ? (ah), (ext + 1) ? (al) ( (ep) ) ? (ah),( (ep) + 1) ? (al) (ep) ? (a) (a) ? d16 (ah) ? (dir), (al) ? (dir + 1) (ah) ? ( (ix) +off), (al) ? ( (ix) +off + 1) (ah) ? (ext), (al) ? (ext + 1) (ah) ? ( (a) ), (al) ? ( (a) ) + 1) (ah) ? ( (ep) ), (al) ? ( (ep) + 1) (a) ? (ep) (ep) ? d16 (ix) ? (a) (a) ? (ix) (sp) ? (a) (a) ? (sp) ( (a) ) ? (t) ( (a) ) ? (th),( (a) + 1) ? (tl) (ix) ? d16 (a) ? (ps) (ps) ? (a) (sp) ? d16 (ah) ? (al) (dir): b ? 1 (dir): b ? 0 (al) ? (tl) (a) ? (t) (a) ? (ep) (a) ? (ix) (a) ? (sp) (a) ? (pc) C C C C C al al al al al al al C C C C C C C C C al al al al al al C C C C C C C C C C C C C C C al al C C C C C C C C C C C C C C C C C C C C C C C C C ah ah ah ah ah ah C C C C C C C C C C C C C C C C ah C C C C C C C C C C C C C C C C C C C C C C C C C dh dh dh dh dh dh dh C C dh C dh C C C dh C C al C C C dh dh dh dh dh C C C C C C C C C C C C C C C C C C C C + + C C + + C C + + C C + + C C + + C C + + C C + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + C C + + C C + + C C + + C C + + C C + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 45 46 61 47 48 to 4f 04 05 06 60 92 07 08 to 0f 85 86 87 88 to 8f d5 d6 d4 d7 e3 e4 c5 c6 c4 93 c7 f3 e7 e2 f2 e1 f1 82 83 e6 70 71 e5 10 a8 to af a0 to a7 42 43 f7 f6 f5 f0
52 mb89640 series table 3 arithmetic operation instructions (62 instructions) (continued) mnemonic ~ # operation tl th ah n z v c op code addc a,ri addc a,#d8 addc a,dir addc a,@ix +off addc a,@ep addcw a addc a subc a,ri subc a,#d8 subc a,dir subc a,@ix +off subc a,@ep subcw a subc a inc ri incw ep incw ix incw a dec ri decw ep decw ix decw a mulu a divu a andw a orw a xorw a cmp a cmpw a rorc a rolc a cmp a,#d8 cmp a,dir cmp a,@ep cmp a,@ix +off cmp a,ri daa das xor a xor a,#d8 xor a,dir xor a,@ep xor a,@ix +off xor a,ri and a and a,#d8 and a,dir 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 2 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 (a) ? (a) + (ri) + c (a) ? (a) + d8 + c (a) ? (a) + (dir) + c (a) ? (a) + ( (ix) +off) + c (a) ? (a) + ( (ep) ) + c (a) ? (a) + (t) + c (al) ? (al) + (tl) + c (a) ? (a) - (ri) - c (a) ? (a) - d8 - c (a) ? (a) - (dir) - c (a) ? (a) - ( (ix) +off) - c (a) ? (a) - ( (ep) ) - c (a) ? (t) - (a) - c (al) ? (tl) - (al) - c (ri) ? (ri) + 1 (ep) ? (ep) + 1 (ix) ? (ix) + 1 (a) ? (a) + 1 (ri) ? (ri) - 1 (ep) ? (ep) - 1 (ix) ? (ix) - 1 (a) ? (a) - 1 (a) ? (al) (tl) (a) ? (t) / (al),mod ? (t) (a) ? (a) (t) (a) ? (a) (t) (a) ? (a) " (t) (tl) - (al) (t) - (a) (a) - d8 (a) - (dir) (a) - ( (ep) ) (a) - ( (ix) +off) (a) - (ri) decimal adjust for addition decimal adjust for subtraction (a) ? (al) " (tl) (a) ? (al) " d8 (a) ? (al) " (dir) (a) ? (al) " ( (ep) ) (a) ? (al) " ( (ix) +off) (a) ? (al) " (ri) (a) ? (al) (tl) (a) ? (al) d8 (a) ? (al) (dir) C C C C C C C C C C C C C C C C C C C C C C C dl C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 00 C C C C C C C C C C C C C C C C C C C C C C C C C C C C dh C C C C C C dh C C C C dh C C C dh dh 00 dh dh dh C C C C C C C C C C C C C C C C C C C C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + C C C C C C C C C + + C C + + + C C C C C C C C C + + C C C C C C C C C C + + r C + + r C + + r C + + + + + + + + + + C + + + C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C 28 to 2f 24 25 26 27 23 22 38 to 3f 34 35 36 37 33 32 c8 to cf c3 c2 c0 d8 to df d3 d2 d0 01 11 63 73 53 12 13 03 02 14 15 17 16 18 to 1f 84 94 52 54 55 57 56 58 to 5f 62 64 65 a c ? ? ?? a c
53 mb89640 series (continued) table 4 branch instructions (17 instructions) table 5 other instructions (9 instructions) mnemonic ~ # operation tl th ah n z v c op code and a,@ep and a,@ix +off and a,ri or a or a,#d8 or a,dir or a,@ep or a,@ix +off or a,ri cmp dir,#d8 cmp @ep,#d8 cmp @ix +off,#d8 cmp ri,#d8 incw sp decw sp 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 (a) ? (al) ( (ep) ) (a) ? (al) ( (ix) +off) (a) ? (al) (ri) (a) ? (al) (tl) (a) ? (al) d8 (a) ? (al) (dir) (a) ? (al) ( (ep) ) (a) ? (al) ( (ix) +off) (a) ? (al) (ri) (dir) C d8 ( (ep) ) C d8 ( (ix) + off) C d8 (ri) C d8 (sp) ? (sp) + 1 (sp) ? (sp) C 1 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + + + + + + + + + + + + + + + C C C C C C C C 67 66 68 to 6f 72 74 75 77 76 78 to 7f 95 97 96 98 to 9f c1 d1 mnemonic ~ # operation tl th ah n z v c op code bz/beq rel bnz/bne rel bc/blo rel bnc/bhs rel bn rel bp rel blt rel bge rel bbc dir: b,rel bbs dir: b,rel jmp @a jmp ext callv #vct call ext xchw a,pc ret reti 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 if z = 1 then pc ? pc + rel if z = 0 then pc ? pc + rel if c = 1 then pc ? pc + rel if c = 0 then pc ? pc + rel if n = 1 then pc ? pc + rel if n = 0 then pc ? pc + rel if v " n = 1 then pc ? pc + rel if v " n = 0 then pc ? pc + rei if (dir: b) = 0 then pc ? pc + rel if (dir: b) = 1 then pc ? pc + rel (pc) ? (a) (pc) ? ext vector call subroutine call (pc) ? (a),(a) ? (pc) + 1 return from subrountine return form interrupt C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C dh C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + C C C + C C C C C C C C C C C C C C C C C C C C C C C C C C restore fd fc f9 f8 fb fa ff fe b0 to b7 b8 to bf e0 21 e8 to ef 31 f4 20 30 mnemonic ~ # operation tl th ah n z v c op code pushw a popw a pushw ix popw ix nop clrc setc clri seti 4 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C C C C C C C C C C C C C C C C C C C dh C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C r C C C s C C C C C C C C 40 50 41 51 00 81 91 80 90
54 mb89640 series n instruction map 0123456789abcdef 0 nop swap ret reti pushw a popw a mov a,ext movw a,ps clri seti clrb dir: 0 bbc dir: 0,rel incw a decw a jmp @a movw a,pc 1 mulu a divu a jmp addr16 call addr16 pushw ix popw ix mov ext,a movw ps,a clrc setc clrb dir: 1 bbc dir: 1,rel incw sp decw sp movw sp,a movw a,sp 2 rolc a cmp a addc a subc a xch a, t xor a and a or a mov @a,t mov a,@a clrb dir: 2 bbc dir: 2,rel incw ix decw ix movw ix,a movw a,ix 3 rorc a cmpw a addcw a subcw a xchw a, t xorw a andw a orw a movw @a,t movw a,@a clrb dir: 3 bbc dir: 3,rel incw ep decw ep movw ep,a movw a,ep 4 mov a,#d8 cmp a,#d8 addc a,#d8 subc a,#d8 xor a,#d8 and a,#d8 or a,#d8 daa das clrb dir: 4 bbc dir: 4,rel movw a,ext movw ext,a movw a,#d16 xchw a,pc 5 mov a,dir cmp a,dir addc a,dir subc a,dir mov dir,a xor a,dir and a,dir or a,dir mov dir,#d8 cmp dir,#d8 clrb dir: 5 bbc dir: 5,rel movw a,dir movw dir,a movw sp,#d16 xchw a,sp 6 mov a,@ix +d cmp a,@ix +d addc a,@ix +d subc a,@ix +d mov @ix +d,a xor a,@ix +d and a,@ix +d or a,@ix +d mov @ix +d,#d8 cmp @ix +d,#d8 clrb dir: 6 bbc dir: 6,rel movw a,@ix +d movw @ix +d,a movw ix,#d16 xchw a,ix 7 mov a,@ep cmp a,@ep addc a,@ep subc a,@ep mov @ep,a xor a,@ep and a,@ep or a,@ep mov @ep,#d8 cmp @ep,#d8 clrb dir: 7 bbc dir: 7,rel movw a,@ep movw @ep,a movw ep,#d16 xchw a,ep 8 mov a,r0 cmp a,r0 addc a,r0 subc a,r0 mov r0,a xor a,r0 and a,r0 or a,r0 mov r0,#d8 cmp r0,#d8 setb dir: 0 bbs dir: 0,rel inc r0 dec r0 callv #0 bnc rel 9 mov a,r1 cmp a,r1 addc a,r1 subc a,r1 mov r1,a xor a,r1 and a,r1 or a,r1 mov r1,#d8 cmp r1,#d8 setb dir: 1 bbs dir: 1,rel inc r1 dec r1 callv #1 bc rel a mov a,r2 cmp a,r2 addc a,r2 subc a,r2 mov r2,a xor a,r2 and a,r2 or a,r2 mov r2,#d8 cmp r2,#d8 setb dir: 2 bbs dir: 2,rel inc r2 dec r2 callv #2 bp rel b mov a,r3 cmp a,r3 addc a,r3 subc a,r3 mov r3,a xor a,r3 and a,r3 or a,r3 mov r3,#d8 cmp r3,#d8 setb dir: 3 bbs dir: 3,rel inc r3 dec r3 callv #3 bn rel c mov a,r4 cmp a,r4 addc a,r4 subc a,r4 mov r4,a xor a,r4 and a,r4 or a,r4 mov r4,#d8 cmp r4,#d8 setb dir: 4 bbs dir: 4,rel inc r4 dec r4 callv #4 bnz rel d mov a,r5 cmp a,r5 addc a,r5 subc a,r5 mov r5,a xor a,r5 and a,r5 or a,r5 mov r5,#d8 cmp r5,#d8 setb dir: 5 bbs dir: 5,rel inc r5 dec r5 callv #5 bz rel e mov a,r6 cmp a,r6 addc a,r6 subc a,r6 mov r6,a xor a,r6 and a,r6 or a,r6 mov r6,#d8 cmp r6,#d8 setb dir: 6 bbs dir: 6,rel inc r6 dec r6 callv #6 bge rel f mov a,r7 cmp a,r7 addc a,r7 subc a,r7 mov r7,a xor a,r7 and a,r7 or a,r7 mov r7,#d8 cmp r7,#d8 setb dir: 7 bbs dir: 7,rel inc r7 dec r7 callv #7 blt rel l h
55 mb89640 series n mask options n ordering information no. part number mb89643 mb89645 mb89646 mb89647 MB89P647 mb89pv640 specifying procedure specify when ordering masking set with eprom programmer setting not possible 1 pull-up resistors p00 to p07, p10 to p17, p30 to p37, p40 to p47, p50 to p57, p60 to p67, p70 to p74, p80 to p83 selectable per pin (p60 to p67 must be set to without a pull-up resistor when an a/d converter is used. p51 and p50 are must be set to without a pull-up resistor when a d/a converter is used.) can be set per pin (only p40 to p47 and p50 to p57 are without a pull- up resistor.) fixed to without pull-up resistor 2 power-on reset with power-on reset without power-on reset selectable setting possible fixed to with power-on reset 3 main clock oscillation stabilization time selection (when operating at 10 mhz) approx. 2 18 /f ch (approx. 26.2 ms) approx. 2 17 /f ch (approx. 13.1 ms) approx. 2 14 /f ch (approx. 1.6 ms) approx. 2 4 /f ch (approx. 0 ms) f ch : main clock frequency selectable setting possible fixed to approx. 2 18 /f ch (approx. 26.2 ms) 4 reset pin output with reset output without reset output selectable setting possible fixed to with reset output 5 selection either single- or dual-clock system single clock dual clock selectable setting possible fixed to dual- clock system part number package remarks mb89647pfm mb89646pfm mb89645pfm mb89643pfm MB89P647pfm 80-pin plastic qfp (fpt-80p-m11) mb89647pf mb89646pf mb89645pf mb89643pf MB89P647pf 80-pin plastic qfp (fpt-80p-m06) mb89pv640cf 80-pin ceramic mqfp (mqp-80c-p01)
56 mb89640 series n package dimensions 80-pin plastic qfp (fpt-80p-m11) dimensions in mm (inches) C.001 +.002 C0.02 +0.05 +0.20 C0.10 +.008 C.004 lead no. 60 41 61 80 1 40 21 20 nom (.591) ref (.486) 15.00 12.35 .005 0.127 (.012.004) 0.300.10 0.65(.0256)typ 14.000.10(.551.004)sq 16.000.20(.630.008)sq (stand off) (.020.008) (.004.004) 0.100.10 0.500.20 0 10 details of "a" part "a" 1.50 .059 1 pin index 0.10(.004) m 0.13(.005) 1994 fujitsu limited f80016s-1c-2 c
57 mb89640 series 80-pin plastic qfp (fpt-80p-m06) dimensions in mm (inches) "a" lead no. (.031.008) 0.800.20 0.30(.012) 0.25(.010) 80 65 64 41 40 25 24 1 22.300.40(.878.016) 18.40(.724)ref m 0.16(.006) (.014.004) 0.350.10 0.80(.0315)typ (.705.016) (.551.008) 14.000.20 17.900.40 20.000.20(.787.008) 23.900.40(.941.016) index 0.150.05(.006.002) (stand off) 0.05(.002)min 3.35(.132)max (.642.016) 16.300.40 ref 12.00(.472) details of "b" part 0 10 details of "a" part 0.18(.007)max 0.58(.023)max 0.10(.004) "b" 1994 fujitsu limited f80010s-3c-2 c
58 mb89640 series 80-pin ceramic mqfp (mqp-80c-p01) dimensions in mm (inches) +0.40 C0.20 +.016 C.008 +0.40 C0.20 +.016 C.008 index typ 4.50(.177) typ 6.00(.236) index area 1.50(.059)typ 1.00(.040)typ typ 1.00(.040) typ 1.50(.059) (.0315.010) 0.800.25 1.20 .047 12.00(.472)typ (.0315.010) 0.800.25 ref 18.40(.724) (.016.004) 0.400.10 1.20 .047 (.016.004) 0.400.10 max 8.70(.343) (.006.002) 0.150.05 11.68(.460)typ 9.48(.373)typ 7.62(.300)typ 0.30(.012)typ (.050.005) 1.270.13 (.713.008) 18.120.20 typ 14.22(.560) typ 12.02(.473) typ 10.16(.400) typ 24.70(.972) (.878.013) 22.300.33 (.050.005) 1.270.13 typ 0.30(.012) index area 18.70(.736)typ (.642.013) 16.300.33 (.613.008) 15.580.20 1994 fujitsu limited m80001sc-4-2 c
59 mb89640 series fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka, nakahara-ku, kawasaki-shi, kanagawa 211-8588, japan tel: +81-44-754-3763 fax: +81-44-754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. 3545 north first street, san jose, ca 95134-1804, u.s.a. tel: +1-408-922-9000 fax: +1-408-922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: +1-800-866-8608 fax: +1-408-922-9179 http://www.fujitsumicro.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fujitsu-fme.com/ asia pacific fujitsu microelectronics asia pte. ltd. #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-281-0770 fax: +65-281-0220 http://www.fmap.com.sg/ korea fujitsu microelectronics korea ltd. 1702 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 f0005 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the contents of this document may not be reproduced or copied without the permission of fujitsu limited. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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